SC312XDP512F0MPVR datasheet(101/1348 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

101

The clock generator creates the clocks used in the MCU (see Figure 2-17). The gating condition placed on

top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the

setting of the respective conﬁguration bits.

The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The

memory blocks use the bus clock. If the MCU enters self clock mode (see Section 2.4.2.2, “Self Clock

Mode”) oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The bus

clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.

The core clock is twice the bus clock as shown in Figure 2-18. But note that a CPU cycle corresponds to

one bus clock.

PLL clock mode is selected with PLLSEL bit in the CLKSEL registerr. When selected, the PLL output

clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned

off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum

of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and

CPU activity ceases.

Figure 2-18. Core Clock and Bus Clock Relationship

2.4.1.3

Clock Monitor (CM)

If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block

generates a clock monitor fail event. The CRG then asserts self clock mode or generates a system reset

depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected

no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME

control bit.

2.4.1.4

Clock Quality Checker

The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker

provides a more accurate check in addition to the clock monitor.

A clock quality check is triggered by any of the following events:

•

Power on reset (POR)

•

Low voltage reset (LVR)

•

Wake-up from full stop mode (exit full stop)

•

Clock monitor fail indication (CM fail)

A time window of 50,000 VCO clock cycles1 is called check window.

1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM.

CORE CLOCK

BUS CLOCK / ECLK

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