SC312XDP512F0MPVR datasheet(974/1348 Pages) FREESCALE

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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

976

Freescale Semiconductor

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Data and data direction registers for Ports A, B, E, K, T, S, M, P, H, J, and AD1 when used as

general-purpose I/O

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Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,

H, and J on per-pin basis

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Control registers to enable/disable pull-up devices on Port AD1 on per-pin basis

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Single control register to enable/disable pull-ups on Ports A, B, E, and K on per-port basis and on

BKGD pin

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Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, and AD1 on per-

pin basis

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Single control register to enable/disable reduced output drive on Ports A, B, E, and K on per-port

basis

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Control registers to enable/disable open-drain (wired-OR) mode on Ports S and M

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Control registers to enable/disable pin interrupts on Ports P, H, and J

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Interrupt flag register for pin interrupts on Ports P, H, and J

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Control register to configure IRQ pin operation

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Free-running clock outputs

A standard port pin has the following minimum features:

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Input/output selection

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5V output drive with two selectable drive strengths

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5V digital and analog input

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Input with selectable pull-up or pull-down device

Optional features:

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Open drain for wired-OR connections

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Interrupt inputs with glitch filtering

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Reduced input threshold to support low voltage applications

24.0.2

Block Diagram

Figure 24-1 is a block diagram of the PIM.

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Signals shown in Bold are not available in 80-pin packages.

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Shaded labels denote alternative module routing ports.

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