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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 962 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 962 Page - Freescale Semiconductor, Inc |
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962 / 1348 page  Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 964 Freescale Semiconductor Figure 23-76. Illustration of I/O Pin Functionality 23.0.6.4 Reduced Drive Register If the pin is used as an output this register allows the configuration of the drive strength. 23.0.6.5 Pull Device Enable Register This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-OR output. 23.0.6.6 Polarity Select Register This register selects either a pull-up or pull-down device if enabled. It becomes active only if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-OR output. If the pin is used as an interrupt input this register selects the active interrupt edge. 23.0.6.7 Wired-OR Mode Register If the pin is used as an output this register turns off the active high drive. This allows wired-OR type connections of outputs. 23.0.6.8 Interrupt Enable Register If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 23.0.6.9 Interrupt Flag Register If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. PT DDR output enable module enable 1 0 1 1 0 0 PIN PTI data out Module |
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