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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 876 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 876 Page - Freescale Semiconductor, Inc |
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876 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 878 Freescale Semiconductor 22.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[15:08] as either input or output. 76543210 R DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18 W Reset 00000000 Figure 22-71. Port AD1 Data Direction Register 1 (DDR1AD1) Table 22-62. DDR1AD1 Field Descriptions Field Description 7–0 DDR1AD1[15:8] Data Direction Port AD1 Register 1 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTAD11 register, when changing the DDR1AD1 register. Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has to be set to logic level “1”. |
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