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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 849 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 849 Page - Freescale Semiconductor, Inc |
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849 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 851 22.3.2.32 Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output. The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output (TXCAN[3:0], TXD3). TheyAlso forces the I/O state to be an input for each port line associated with an enabled input (RXCAN[3:0], RXD3). In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 76543210 R DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 W Reset 00000000 Figure 22-34. Port M Data Direction Register (DDRM) Table 22-33. DDRM Field Descriptions Field Description 7–0 DDRM[7:0] Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. |
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