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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 843 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 843 Page - Freescale Semiconductor, Inc |
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843 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 845 22.3.2.25 Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 76543210 R DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W Reset 00000000 Figure 22-27. Port S Data Direction Register (DDRS) Table 22-27. DDRS Field Descriptions Field Description 7–0 DDRS[7:0] Data Direction Port S 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register. |
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