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SC312XDP512F0MPVR датащи(PDF) 809 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 809 Page - Freescale Semiconductor, Inc |
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809 / 1348 page ![]() Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 811 E PE[7] XCLKS1 I External clock selection input during RESET Mode dependent3 ECLKX2 I Free-running clock output at Core Clock rate (ECLK x 2) GPIO I/O General-purpose I/O PE[6] MODB1 I MODB input during RESET TAGHI I Instruction tagging low pin Configurable for reduced input threshold GPIO I/O General-purpose I/O PE[5] MODA1 I MODA input during RESET RE O Read enable signal TAGLO I Instruction tagging low pin Configurable for reduced input threshold GPIO I/O General-purpose I/O PE[4] ECLK O Free-running clock output at the Bus Clock rate or programmable divided in normal modes GPIO I/O General-purpose I/O PE[3] EROMCTL1 I EROMON bit control input during RESET LSTRB O Low strobe bar output LDS O Lower data strobe GPIO I/O General-purpose I/O PE[2] R/W O Read/write output for external bus WE O Write enable signal GPIO I/O General-purpose I/O PE[1] IRQ I Maskable level- or falling edge-sensitive interrupt input GPIO I/O General-purpose I/O PE[0] XIRQ I Non-maskable level-sensitive interrupt input GPIO I/O General-purpose I/O Table 22-1. Pin Functions and Priorities (Sheet 2 of 7) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset |
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