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Chapter 16 Interrupt (S12XINTV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

608

Freescale Semiconductor

16.4.2.1

Interrupt Priority Stack

The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This

way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The

new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel

which is conﬁgured to be handled by the CPU. The copying takes place when the interrupt vector is

fetched. The previous IPL is automatically restored by executing the RTI instruction.

16.4.3

XGATE Requests

The XINT module processes all exception requests to be serviced by the XGATE module. The overall

priority level of those exceptions is discussed in the subsections below.

16.4.3.1

XGATE Request Prioritization

An interrupt request channel is conﬁgured to be handled by the XGATE module, if the RQST bit of the

associated conﬁguration register is set to 1 (please refer to Section 16.3.1.4, “Interrupt Request

Conﬁguration Data Registers (INT_CFDATA0–7)”). The priority level setting (PRIOLVL) for this channel

becomes the DMA priority which will be used to determine the highest priority DMA request to be

serviced next by the XGATE module. Additionally, DMA interrupts may be raised by the XGATE module

by setting one or more of the XGATE channel interrupt ﬂags (using the SIF instruction). This will result

in an CPU interrupt with vector address vector base + (2 * channel ID number), where the channel ID

number corresponds to the highest set channel interrupt ﬂag, if the XGIE and channel RQST bits are set.

The shared interrupt priority for the DMA interrupt requests is taken from the XGATE interrupt priority

conﬁguration register (please refer to Section 16.3.1.2, “XGATE Interrupt Priority Conﬁguration Register

(INT_XGPRIO)”). If more than one DMA interrupt request channel becomes active at the same time, the

channel with the highest vector address wins the prioritization.

16.4.4

Priority Decoders

The XINT module contains priority decoders to determine the priority for all interrupt requests pending

for the respective target.

There are two priority decoders, one for each interrupt request target (CPU, XGATE module). The function

of both priority decoders is basically the same with one exception: the priority decoder for the XGATE

module does not take the current interrupt processing level into account because XGATE requests cannot

be nested.

Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt

request could override the original exception that caused the CPU to request the vector. In this case, the

CPU will receive the highest priority vector and the system will process this exception instead of the

original request.

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