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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 585 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 585 Page - Freescale Semiconductor, Inc |
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585 / 1348 page  Chapter 15 Background Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 585 Figure 15-8. BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 15-9 shows the host receiving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. Figure 15-9. BDM Target-to-Host Serial Bit Timing (Logic 1) Target Senses Bit 10 Cycles Synchronization Uncertainty BDM Clock (Target MCU) Host Transmit 1 Host Transmit 0 Perceived Start of Bit Time Earliest Start of Next Bit High-Impedance Earliest Start of Next Bit R-C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin Perceived Start of Bit Time BKGD Pin BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse High-Impedance High-Impedance |
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