SC312XDP512F0MPVR datasheet(579/1348 Pages) FREESCALE

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Chapter 15 Background Debug Module (S12XBDMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

579

After being enabled, BDM is activated by one of the following1:

•

Hardware BACKGROUND command

•

CPU BGND instruction

•

External instruction tagging mechanism2

•

Breakpoint force or tag mechanism2

When BDM is activated, the CPU ﬁnishes executing the current instruction and then begins executing the

ﬁrmware in the standard BDM ﬁrmware lookup table. When BDM is activated by a breakpoint, the type

of breakpoint used determines if BDM becomes active before or after execution of the next instruction.

NOTE

If an attempt is made to activate BDM before being enabled, the CPU

resumes normal instruction execution after a brief delay. If BDM is not

enabled, any hardware BACKGROUND commands issued are ignored by

the BDM and the CPU is not delayed.

In active BDM, the BDM registers and standard BDM ﬁrmware lookup table are mapped to addresses

0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses

these registers which are readable anytime by the BDM. However, these registers are not readable by user

programs.

15.4.3

BDM Hardware Commands

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode. Target system memory includes all memory that is accessible by the CPU such

as on-chip RAM, EEPROM, Flash EEPROM, I/O and control registers, and all external memory.

Hardware commands are executed with minimal or no CPU intervention and do not require the system to

be in active BDM for execution, although, they can still be executed in this mode. When executing a

hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not

disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is

momentarily frozen so that the BDM can steal a cycle. When the BDM ﬁnds a free cycle, the operation

does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,

if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the

BDM found a free cycle.

The BDM hardware commands are listed in Table 15-5.

The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations

are not normally in the system memory map but share addresses with the application in memory. To

distinguish between physical memory locations that share the same address, BDM memory resources are

enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM

locations unobtrusively, even if the addresses conﬂict with the application memory map.

1. BDM is enabled and active immediately out of special single-chip reset.

2. This method is provided by the S12X_DBG module.

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