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SC312XDP512F0MPVR датащи(PDF) 502 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 502 Page - Freescale Semiconductor, Inc |
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502 / 1348 page ![]() Chapter 11 Serial Communication Interface (S12SCIV5) MC9S12XDP512 Data Sheet, Rev. 2.21 502 Freescale Semiconductor 11.4.6 Receiver Figure 11-20. SCI Receiver Block Diagram 11.4.6.1 Receiver Character Length The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 11.4.6.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, M WAKE ILT PE PT RE H 876543210L 11-Bit Receive Shift Register Data Wakeup Parity Checking SCI Data Register R8 ILIE RWU RDRF OR NF FE PE Internal Bus Bus SBR12:SBR0 Baud Divider Clock IDLE RAF Recovery Logic RXPOL LOOPS Loop RSRC Control SCRXD From TXD Pin or Transmitter Idle IRQ RDRF/OR IRQ Break Detect Logic Active Edge Detect Logic BRKDFE BRKDIE BRKDIF RXEDGIE RXEDGIF Break IRQ RX Active Edge IRQ RIE |
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