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SC312XDP512F0MPVR датащи(PDF) 481 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 481 Page - Freescale Semiconductor, Inc |
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481 / 1348 page ![]() Chapter 11 Serial Communication Interface (S12SCIV5) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 481 11.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. Register Name Bit 7 6 5 4 3 2 1 Bit 0 SCIBDH1 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W SCIASR12 R RXEDGIF 0000 BERRV BERRIF BKDIF W SCIACR12 R RXEDGIE 00000 BERRIE BKDIE W SCIACR22 R 0 0000 BERRM1 BERRM0 BKDFE W SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W SCISR2 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W SCIDRH R R8 T8 000000 W SCIDRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7T6T5T4T3T2T1T0 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 11-2. SCI Register Summary 1 Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero 2 Those registers are accessible if the AMAP bit in the SCISR2 register is set to one |
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