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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 422 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 422 Page - Freescale Semiconductor, Inc |
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422 / 1348 page  Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.21 422 Freescale Semiconductor Figure 10-2. CAN System 10.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 10.3.1 Module Memory Map Figure 10-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. Register Name Bit 7 6 5 4321 Bit 0 0x0000 CANCTL0 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ W 0x0001 CANCTL1 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary CAN Bus CAN Controller (MSCAN) Transceiver CAN node 1 CAN node 2 CAN node n CAN_L CAN_H MCU TXCAN RXCAN |
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