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SC312XDP512F0MPVR датащи(PDF) 399 Page - Freescale Semiconductor, Inc

номер детали SC312XDP512F0MPVR
подробное описание детали  HCS12X Microcontrollers
PDF  1348 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
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SC312XDP512F0MPVR датащи(HTML) 399 Page - Freescale Semiconductor, Inc

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
399
9.3.2.2
IIC Frequency Divider Register (IBFD)
Read and write anytime
76543210
R
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
W
Reset
00000000
= Unimplemented or Reserved
Figure 9-4. IIC Bus Frequency Divider Register (IBFD)
Table 9-2. IBFD Field Descriptions
Field
Description
7:0
IBC[7:0]
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 9-3.
Table 9-3. I-Bus Tap and Prescale Values
IBC2-0
(bin)
SCL Tap
(clocks)
SDA Tap
(clocks)
000
5
1
001
6
1
010
7
2
011
8
2
100
9
3
101
10
3
110
12
4
111
15
4
IBC5-3
(bin)
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
000
2741
001
2742
010
2964
011
6968
100
14
17
14
16
101
30
33
30
32
110
62
65
62
64
111
126
129
126
128



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