SC312XDP512F0MPVR datasheet(358/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

358

Freescale Semiconductor

If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding

This will prevent the captured value from being overwritten until it is read or latched in the holding

2. IC Queue Mode (LATQ = 0)

The main timer value is memorized in the IC register by a valid input pin transition (see Figure 7-67

and Figure 7-68).

If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a

capture, the value of the IC register will be transferred to its holding register and the IC register

memorizes the new timer value.

If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding

In queue mode, reads of the holding register will latch the corresponding pulse accumulator value

to its holding register.

7.4.1.1.3

Delayed IC Channels

There are four delay counters in this module associated with IC channels 0–3. The use of this feature is

explained in the diagram and notes below.

Figure 7-72. Channel Input Validity with Delay Counter Feature

In Figure 7-72 a delay counter value of 256 bus cycles is considered.

1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.

2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or

accepted, depending on their relative alignment with the sample points.

3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or

accepted, depending on their relative alignment with the sample points.

4. Input pulses with a duration of DLY_CNT or longer are accepted.

253

254

255

256

BUS CLOCK

DLY_CNT

INPUT ON

CH0–3

Rejected

Accepted

INPUT ON

CH0–3

INPUT ON

CH0–3

Accepted

INPUT ON

CH0–3

Rejected

255 Cycles

255.5 Cycles

256 Cycles

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