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SC312XDP512F0MPVR датащи(PDF) 267 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 267 Page - Freescale Semiconductor, Inc |
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267 / 1348 page ![]() Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 267 Operation RS1 | RS2 ⇒ RD RD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16 bit values and stores the result in the destination register RD. CCR Effects Code and CPU Cycles OR Logical OR OR NZ V C ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. Refer to ORH instruction for #IMM16 operations. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles OR RD, RS1, RS2 TRI 0 0 0 1 0 RD RS1 RS2 1 0 P OR RD, #IMM16 IMM8 1 0 1 0 0 RD IMM16[7:0] P IMM8 1 0 1 0 1 RD IMM16[15:8] P |
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