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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 223 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 223 Page - Freescale Semiconductor, Inc |
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223 / 1348 page  Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 223 Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS is greater than 15. CCR Effects Code and CPU Cycles ASR Arithmetic Shift Right ASR NZ V C ∆∆ 0 ∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Source Form Address Mode Machine Code Cycles ASR RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 0 0 1 P ASR RD, RS DYA 0 0 0 0 1 RD RS 1 0 0 0 1 P b15 RD C n |
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