68HC705SB7 datasheet(6/170 Pages) FREESCALE

6 / 170 page

GENERAL RELEASE SPECIFICATION

August 27, 1998

MOTOROLA

MC68HC05SB7

REV 2.1

TABLE OF CONTENTS

Section

Page

SECTION 12

SM-BUS

12.1

SM-BUS INTRODUCTION............................................................................. 12-1

12.2

SM-BUS INTERFACE FEATURES................................................................ 12-1

12.3

SM-BUS SYSTEM CONFIGURATION .......................................................... 12-2

12.4

SM-BUS PROTOCOL .................................................................................... 12-2

12.4.1

START Signal ............................................................................................ 12-3

12.4.2

Slave Address Transmission ..................................................................... 12-3

12.4.3

Data Transfer............................................................................................. 12-3

12.4.4

Repeated START Signal ........................................................................... 12-4

12.4.5

STOP Signal .............................................................................................. 12-4

12.4.6

Arbitration Procedure................................................................................. 12-4

12.4.7

Clock Synchronization ............................................................................... 12-5

12.4.8

Handshaking.............................................................................................. 12-5

12.5

SM-BUS REGISTERS ................................................................................... 12-5

12.5.1

SM-Bus Address Register (SMADR) ......................................................... 12-6

12.5.2

SM-Bus Frequency Divider Register (SMFDR) ......................................... 12-6

12.5.3

SM-Bus Control Register (SMCR) ............................................................. 12-7

12.5.4

SM-Bus Status Register (SMSR)............................................................... 12-8

12.5.5

SM-Bus Data I/O Register (SMDR) ......................................................... 12-10

12.5.6

SM-Bus logic Level .................................................................................. 12-10

12.5.7

SCL as16-bit Timer Input Capture ........................................................... 12-10

12.6

PROGRAMMING CONSIDERATIONS........................................................ 12-11

12.6.1

Initialization .............................................................................................. 12-11

12.6.2

Generation of a START Signal and the First Byte of Data Transfer ........ 12-11

12.6.3

Software Responses after Transmission or Reception of a Byte ............ 12-11

12.6.4

Generation of the STOP Signal ............................................................... 12-13

12.6.5

Generation of a Repeated START Signal................................................ 12-14

12.6.6

Slave Mode.............................................................................................. 12-14

12.6.7

Arbitration Lost......................................................................................... 12-14

12.7

OPERATION DURING WAIT MODE ........................................................... 12-14

12.8

OPERATION DURING STOP MODE .......................................................... 12-14

SECTION 13

CURRENT SENSE AMPLIFIER

13.1

CURRENT SENSE AMPLIFIER APPLICATION............................................ 13-1

13.2

CURRENT SENSE INTERRUPT................................................................... 13-2

13.3

CSA STATUS AND CONTROL REGISTER (CSSCR) .................................. 13-2

13.4

CSA OPERATION DURING WAIT MODE..................................................... 13-4

13.5

CSA OPERATION DURING STOP MODE.................................................... 13-4

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