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68HC705SB7 датащи(PDF) 49 Page - Freescale Semiconductor, Inc

номер детали 68HC705SB7
подробное описание детали  SPECIFICATION (General Release)
PDF  170 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

68HC705SB7 датащи(HTML) 49 Page - Freescale Semiconductor, Inc

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August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
LOW POWER MODES
MOTOROLA
REV 2.1
6-5
To put the MCU in the data retention mode:
1.
Drive the RESET pin to a logic zero.
2.
Lower the VDD voltage. The RESET pin must remain low continuously
during data retention mode.
To take the MCU out of the data retention mode:
1.
Return VDD to normal operating voltage.
2.
Return the RESET pin to a logic one.
6.4
SLOW MODE
The Slow Mode feature permits a slow down of all the internal operations and thus
reduces power consumption. It is particularly useful while going to the WAIT
mode. Slow mode is enabled by setting the SCLK bit in the Miscellaneous Control
Register ($0B).
SCLK — Slow Clock
Setting this bit to one will slow down the internal oscillator. Setting this bit to
zero the system will run at the nominal bus speed (fosc/2). This bit is cleared
during power-on or external reset.
1 =
Slow clock selected:
Internal operating frequency, fOP=fBUS=fOSC/1600.
0 =
Normal clock selected:
Internal operating frequency, fOP=fBUS=fOSC/2.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCR
R
TSEN
LVRON
0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
$000B
W
COPON
reset:
01000000
U = UNAFFECTED BY RESET
Figure 6-2. Miscellaneous Control Register (MCR)



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