LTC6909 datasheet(6/20 Pages) LINER

6 / 20 page

LTC6909

6909f

V+A (Pin 1): Analog Voltage Supply (2.7V ≤ V+A ≤ 5.5V).

This supply should be kept free of noise and ripple. It

should be bypassed directly to GND with a 0.1μF or greater

low ESR capacitor. V+A and V+D must be connected to the

same supply voltage.

GND (Pin 2): Ground Connections. Should be tied to a

ground plane for best performance.

PH0, PH1, PH2 (Pins 3, 4, 15): Output Phasing Selec-

tion Pins. These are standard CMOS logic input pins and

they do not have an internal pull-up or pull-down. These

pins must be connected to a valid logic input 0 or 1 volt-

age. Connect the pins to GND for a logic 0 and to the V+D

pin for a logic 1. These pins conﬁgure the output phase

relationships as follows:

PH2

PH1

PH0

MODE

All Outputs Are Floating (Hi-Z)

All Outputs Are Held Low

3-Phase Mode (PH = 3)

4-Phase Mode (PH = 4)

5-Phase Mode (PH = 5)

6-Phase Mode (PH = 6)

7-Phase Mode (PH = 7)

8-Phase Mode (PH = 8)

The PH0, PH1, PH2 pin connections not only determine

the phase relationship of the output signals but also divide

the master oscillator frequency by the value PH.

OUT1 Through OUT8 (Pins 5 Through 12): Oscillator

Outputs. These are CMOS rail-to-rail logic outputs with

a series resistance of approximately 40Ω, capable of

driving 1k and/or 50pF loads. Larger loads may cause

minor frequency inaccuracies due to supply bounce at high

frequencies. When any output pin is not in use, it is in a

ﬂoating, high impedance state. The outputs are also held

in a high impedance state during start-up. After the part’s

internal frequency setting loop has settled, the outputs

are active, clean and operating at the set frequency (ﬁrst

cycle accurate).

V+D (Pin 13):

Digital Voltage Supply (2.7V ≤ V+D ≤ 5.5V).

This pin should be bypassed directly to GND with a 0.1μF

or greater low ESR capacitor. V+D and V+A must be con-

nected to the same supply voltage.

MOD (Pin 14): Spread Spectrum Frequency Modulation

Setting Input. This input selects among four modulation

rate settings. The MOD pin should be tied to ground for

an fOUT/16 modulation rate. Floating the MOD pin selects

an fOUT/32 modulation rate. The MOD pin should be tied

to V+D for the fOUT/64 modulation rate. Tying one of the

active outputs to the MOD pin turns the modulation off.

To detect a ﬂoating MOD pin, the LTC6909 attempts to

pull the pin to the midsupply point. This is realized with

two internal current sources, one tied to V+D and MOD

and the other one tied to GND and MOD. Therefore, driv-

ing the MOD pin high requires sourcing approximately

2μA. Likewise, driving the MOD pin low requires sinking

approximately 2μA. When the MOD pin is ﬂoated for the

fOUT/32 modulation rate, it must be bypassed using a

1nF or larger, capacitor to GND. Any AC signal coupling

to the MOD pin could potentially be detected and stop the

frequency modulation.

SET (Pin 16): Frequency Setting Resistor Input. The value

of the resistor connected between this pin and V+A deter-

mines the frequency of the master oscillator. The output

frequency, fOUT, is the master oscillator frequency divided

by PH as set by the PH0, PH1 and PH2 pin connections.

The voltage on this pin is held approximately 1.1V below

V+A. For best performance, use a precision metal ﬁlm

resistor with a value between 20k and 400k, and limit the

capacitance on the pin to less than 10pF. Resistor values

outside of this range will have some loss of accuracy as

noted in the Electrical Characteristics table.

PIN FUNCTIONS

LTC6909 датащи(PDF) 6 Page - Linear Technology

LTC6909 датащи(HTML) 6 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL