LTC6909 datasheet(8/20 Pages) LINER

8 / 20 page

LTC6909

6909f

IRES (μA)

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.1

100

1000

6909 F01

V+ = 5V

V+ = 3V

TA = 25°C

As shown in the Block Diagram, the LTC6909’s master

oscillator is controlled by the ratio of the voltage between

the V+A and SET pins and the current entering the SET pin

(IMASTER). When the spread spectrum frequency modula-

tion (SSFM) is disabled, IMASTER is strictly determined

by the (V+A – VSET) voltage and the RSET resistor. When

SSFM is enabled, IMASTER is modulated by a ﬁltered pseu-

dorandom noise (PRN) signal. Here the IMASTER current is

a random value uniformly distributed between (ISET – 10%)

and (ISET + 10%). In this way, the frequency is modulated

to produce an approximately ﬂat frequency spectrum,

centered about the set frequency with a bandwidth equal

to approximately 20% of the center frequency.

The voltage on the SET pin is forced to approximately

1.1V below V+A by the PMOS transistor and its gate bias

voltage. This voltage is accurate to ±5% at a particular

input current and supply voltage (see Figure 1). The

LTC6909 is optimized for use with resistors between 20k

and 400k corresponding to master oscillator frequencies

between 500kHz and 10MHz. Accurate master oscillator

frequencies up to 20MHz (RSET = 10k) are attainable if

the supply voltage is greater than 4V. The RSET resistor,

connected between the V+A and SET pins, locks together

the (V+A – VSET) voltage and the current ISET. This allows

the parts to attain excellent frequency accuracy regardless

of the precision of the SET pin. The master oscillation

frequency is:

fMASTER = 20MHz • 10k/RSET

Figure 1. V+ – VSET Variation with IRES

When the spread spectrum frequency modulation (SSFM)

is disabled, the master oscillator frequency is stationary.

When SSFM is enabled, the master oscillator frequency

varies from 0.9 • fMASTER to 1.1 • fMASTER.

Output Frequency and Conﬁgurations

The output frequency of the LTC6909 is set by the RSET

resistor value and the connections of the PH0, PH1 and

PH2 logic input pins. The following formula deﬁnes the

relationship:

fOUT = 20MHz • 10k/(RSET • PH)

where PH = 3, 4, 5, 6, 7 or 8 and is deﬁned as follows:

PH2

PH1

PH0

MODE

All Outputs Are Floating (Hi-Z)

All Outputs Are Held Low

3-Phase Mode (PH = 3)

4-Phase Mode (PH = 4)

5-Phase Mode (PH = 5)

6-Phase Mode (PH = 6)

7-Phase Mode (PH = 7)

8-Phase Mode (PH = 8)

The PH0, PH1 and PH2 pins are standard logic input pins.

These pins do not have any active pull-up or pull-down

circuitry. As such, they cannot be left ﬂoating and must be

connected to a valid logic high or low voltage. The PH0,

PH1 and PH2 pin connections not only divide the master

oscillator frequency by the value PH but also determine

the phase relationship between the output signals. Figure

2 shows the output waveforms for each of the eight pos-

sible output conﬁgurations.

Note that 2-phase, complementary (180° phase shifted)

outputs are available in the 4-, 6- and 8-phase modes

by choosing the correct pair of signals. For example, in

4-phase mode, OUT1 and OUT3 (or OUT2 and OUT4) are

complementary.

OPERATION

LTC6909 датащи(PDF) 8 Page - Linear Technology

LTC6909 датащи(HTML) 8 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL