UJA1076 datasheet(12/47 Pages) NXP

12 / 47 page

UJA1076_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

12 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.2.4 Mode_Control register

[1]

Bit LHWC is set to 1 after a reset.

[2]

Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.

Table 5.

Mode_Control register

Bit

Symbol

Access

Power-on

default

Description

15:13

A2, A1, A0 R

001

R/W

access status

0: register set to read/write

1: register set to read only

11:10

R/W

mode control

00: Standby mode

01: Sleep mode

10: Normal mode; V2 off

11: Normal mode; V2 on

9LHWC[1]

R/W

limp home warning control

0: no limp home warning

1: limp home warning is set; next reset will activate LIMP output

8LHC[2]

R/W

limp home control

0: LIMP pin set floating

1: LIMP pin driven LOW

ENC

R/W

enable control

0: EN pin driven LOW

1: EN pin driven HIGH in Normal mode

reserved

WBC

R/W

wake bias control

0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1

1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1

PDC

R/W

power distribution control

0: V1 threshold current for activating the external PNP transistor; load current

rising; Ith(act)PNP = 85 mA; V1 threshold current for deactivating the external

PNP transistor; load current falling; Ith(deact)PNP =50mA; see Figure 7

1: V1 threshold current for activating the external PNP transistor; load current

rising; Ith(act)PNP = 50 mA; V1 threshold current for deactivating the external

PNP transistor; load current falling; Ith(deact)PNP =15mA; see Figure 7

3:0

reserved

0000

UJA1076 датащи(PDF) 12 Page - NXP Semiconductors

UJA1076 датащи(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

датащи скачать

ссылки URL