ADP3293 datasheet(21/30 Pages) ONSEMI

21 / 30 page

ADP3293

http://onsemi.com

limited to 10% of this (50

mA), the following limit can

be placed for the minimum value for RLL1 and RLL2:

RLL1 ) RLL2 w

ILIM RCSA

10*6

(eq. 15)

Here, ILIM is the current limit current, which is the

maximum signal level that the CSA responds to.

It is best to select the resistor values to minimize their

values to reduce the noise and parasitic susceptibility of the

feedback path.

By combining Equation 14 with Equation 15 and selecting

minimum values for the resistors, the following equations

result:

RLL2 +

ILIM RO

50 mA

(eq. 16)

RLL1 +

RCSA

* 1

RLL2

(eq. 17)

Another useful feature for some VR applications is the

ability to select different load lines. Figure 9 shows an

optional MOSFET switch that allows this feature. Here,

design for RCSA = RO(MAX) (selected with QLL on) and then

use Equation 14 to set RO = RO(MIN) (selected with QLL off).

For this design, RCSA = RO = 1 mW. As a result, connect

LLSET directly to CSCOMP; the RLL1 and RLL2 resistors

are not needed.

Output Offset

The Intel specification requires that at no load the nominal

output voltage of the regulator be offset to a value lower than

the nominal voltage corresponding to the VID code. The

offset is set by a constant current source flowing out of the

FB pin (IFB) and flowing through RB. The value of RB can

be found using Equation 18.

RB +

VVID * VONL

IFB

(eq. 18)

RB +

1.4 V * 1.381 V

15 mA

+ 1.27 kW

The closest standard 1% resistor value is 1.21 k

The required output decoupling for the regulator is

typically recommended by Intel for various processors and

platforms. Use some simple design guidelines to determine

the requirements. These guidelines are based on having both

bulk capacitors and ceramic capacitors in the system.

First, select the total amount of ceramic capacitance. This

is based on the number and type of capacitor to be used. The

best location for ceramic capacitors is inside the socket, with

12 to 18, 1206 size being the physical limit. Other capacitors

can be placed along the outer edge of the socket as well.

To determine the minimum amount of ceramic

capacitance required, start with a worse case load step

occurring right after a switching cycle has stopped. The

ceramic capacitance then delivers the charge to the load

while the load is ramping up and until the VR has responded

with the next switching cycle.

Equation 19 gives the designer a rough approximation for

determining the minimum ceramic capacitance. Due to the

complexity of the PCB parasitics and bulk capacitors, the

actual amount of ceramic capacitance required can vary.

(eq. 19)

CZ(MIN) w 1

fSW

n * D *

D IO

2SR

The typical ceramic capacitors consist of multiple 10

or 22

mF capacitors. For this example, Equation 19 yields

269

mF, so eighteen, 22 mF ceramic capacitors is necessary

(18 pc is the maximum number for existing CPU socket).

Next, there is an upper limit imposed on the total amount

of bulk capacitance (CX) when the user considers the VID

OTF voltage stepping of the output (voltage step VV in time

tV with error of VERR).

A lower limit is based on meeting the capacitance for load

release for a given maximum load step (

DIO) and a

maximum allowable overshoot. The total amount of load

release voltage is given as

DVO = DIO × RO + DVrl, where

DVrl is the maximum allowable overshoot voltage.

(eq. 20)

CX(MIN) w

D IO

RO )

D Vrl

D IO

VVID

* CZ

nK2R2O

VVID

1 ) tV

VVID

nKRO

* 1 * CZ

(eq. 21)

CX(MAX) v

where : K +* 1n

VERR

To meet the conditions of these equations and transient

response, the ESR of the bulk capacitor bank (RX) should be

less than two times the droop resistance (RO). If the CX(MIN)

is larger than CX(MAX), the system cannot meet the VID

OTF specification and can require the use of a smaller

inductor or more phases (and may have to increase the

switching frequency to keep the output ripple the same).

This example uses 18, 22

mF 1206 MLC capacitors

(CZ = 396 mF). The VID OTF step change is 1.1 V in

233.75

ms with a settling error of 5 mV. The maximum

allowable load release overshoot for this example is 50 mV,

therefore, solving for the bulk capacitance yields.

ADP3293 датащи(PDF) 21 Page - ON Semiconductor

ADP3293 датащи(HTML) 21 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

датащи скачать

ссылки URL