LT3071EUFD datasheet(15/28 Pages) LINER

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LT3071

3071f

ApplicAtions inFormAtion

FPGAandASICprocessorsaresufficienttostabilizethe

system(seeStabilityandOutputCapacitancesection).This

regulatordesignprovidesamplebandwidthandresponds

totransientloadchangesinafewhundrednanoseconds

versusregulatorsthatrespondinmanymicroseconds.

TheLT3071alsoincorporatesprecisioncurrentlimiting,

enable/disablecontrolofoutputvoltageandintegrated

overvoltage and thermal shutdown protection. The

LT3071’s unique design combines the benefits of low

dropout voltage, high functional integration, precision

performanceandUltraFasttransientresponse,aswellas

providingsignificantcostsavingsontheoutputcapacitance

neededinfastloadtransientapplications.

Aslowervoltageapplicationsbecomeincreasinglypreva-

lentwithhigherfrequencyswitchingpowersupplies,the

LT3071 offers superior regulation and an appreciable

componentcostsavings.TheLT3071stepstothenext

levelofperformanceforthelatestgenerationFPGAs,DSPs

andmicroprocessors.Thesimpleversatilityandbenefits

derivedfromthesecircuitsexceedthepowersupplyneeds

oftoday’shighperformancemicroprocessors.

Programming Output Voltage

Threetri-levelinputpins,VO2,VO1andVO0,selectthe

valueofoutputvoltage.Table1illustratesthe3-bitdigital

wordtooutputvoltageresultingfromsettingthesepins

high,loworallowingthemtofloat.

Thesepinsmaybetied

highorlowbyeitherpin-strapping

themtoVBIASordrivingthemwithdigitalports.Pinsthat

floatmayeitheractuallyfloatorrequirelogicthathas

Hi-Zoutputcapability.Thisallowsoutputvoltagetobe

dynamicallychangedifnecessary.

Outputvoltageisselectablefromaminimumof0.8Vto

amaximumof1.8Vinincrementsof50mV.TheMSB,

VO2,setsthepedestalvoltage,andtheLSB’s,VO1and

VO0incrementVOUT.

Outputvoltageislimitedto1.8Vmaximumbyaninternal

overrideofVO1(defaulttolow)whenVO2=high.

Table 1: VO2 to VO0 Settings vs Output Voltage

VO2 VO1 VO0

VOUT(NOM)

VO2 VO1 VO0

VOUT(NOM)

0.80V

1.35V

0.85V

1.40V

0.90V

1.45V

0.95V

1.50V

1.00V

1.55V

1.05V

1.60V

1.10V

1.65V

1.15V

1.70V

1.20V

1.75V

1.25V

1.80V

1.30V

X=Don’tCare,0=Low,Z=Float,1=High

Theinputlogiclowthresholdislessthan250mVrefer-

encedtoGNDandthelogichighthresholdisgreaterthan

VBIAS–250mV.Therangebetweenthesetwothresholds

as set by a window comparator defines the logicHi-Z

state.

REF/BYP—Voltage Reference

Thispinisthebufferedoutputoftheinternalbandgap

referenceandhasanoutputimpedanceof

≅19kΩ.The

designincludesaninternalcompensationpoleatfC=4kHz.

A10nFREF/BYPcapacitortoGNDcreatesalowpasspole

atfLP=840Hz.The10nFcapacitordecreasesreference

voltagenoisetoabout10µVRMSandsoft-startstherefer-

ence.TheLT3071onlysoft-startsthereferencevoltage

duringaninitialturn-onsequence.IftheENpinistoggled

lowafterinitialturn-on,thereferenceremainspowered-up.

Therefore,togglingtheENpinfromlowtohighdoesnot

soft-startthereference.OnlybyturningtheBIASsupply

voltageonandoffwillthereferencebesoft-started.Output

voltagenoiseistheRMSsumofthereferencevoltage

noiseinadditiontotheamplifiernoise.

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