TUSB9260

SLLS962A – DECEMBER 2009 – REVISED JULY 2010

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6

CLOCK CONNECTIONS

6.1

Clock Source Requirements

The TUSB9260 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead

of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a

crystal is used, the connection needs to follow the guidelines below.

Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short

as possible and away from any switching leads. It is also recommended to minimize the capacitance

be-tween XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external

capaci-tors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be

connected to PCB ground when using a crystal.

entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2

in Figure 6-1. The trace length between the decoupling capacitors and the corresponding power pins on

the TUSB9260 needs to be minimized. It is also recommended that the trace length from the capacitor

pad to the power or ground plane be minimized.

Figure 6-1. Typical Crystal Connections

6.2

Clock Source Selection Guide

Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the

trans-mit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing

system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock

detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter

reference clock is required to achieve compliance with supported USB3.0 standards. For example,

USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random

phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of

additional jitter compo-nents, the Reference Clock jitter must be considerably below the overall jitter

budget.

16

CLOCK CONNECTIONS

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