PIC16F631-ESLASHML datasheet(34/306 Pages) MICROCHIP

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PIC16F631/677/685/687/689/690

DS41262E-page 32

TABLE 2-1:

PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Page

Bank 0

00h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx

44,205

01h

TMR0

Timer0 Module Register

xxxx xxxx

81,205

02h

PCL

Program Counter’s (PC) Least Significant Byte

0000 0000

44,205

03h

STATUS

IRP

RP1

RP0

ZDC

0001 1xxx

36,205

04h

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

44,205

05h

PORTA(7)

—

RA5

RA4

RA3

RA2

RA1

RA0

--xx xxxx

59,205

06h

PORTB(7)

RB7

RB6

RB5

RB4

—

xxxx ----

69,205

07h

PORTC(7)

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

76,205

08h

—

Unimplemented

—

09h

—

Unimplemented

—

0Ah

PCLATH

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

44,205

0Bh

INTCON

GIE

PEIE

T0IE

INTE

RABIE

T0IF

INTF

RABIF(1)

0000 000x

38,205

0Ch

PIR1

—ADIF(4)

RCIF(2)

TXIF(2)

SSPIF(5)

CCP1IF(3) TMR2IF(3)

TMR1IF

-000 0000

41,205

0Dh

PIR2

OSFIF

C2IF

C1IF

EEIF

—

0000 ----

42,205

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

86,205

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

86,205

10h

T1CON

T1GINV

TMR1GE

T1CKPS1

T1CKPS0 T1OSCEN

T1SYNC

TMR1CS

TMR1ON 0000 0000

88,205

11h

TMR2(3)

Timer2 Module Register

0000 0000

91,205

12h

T2CON(3)

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

TMR2ON

T2CKPS1 T2CKPS0 -000 0000

92,205

13h

SSPBUF(5)

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

182,205

14h

SSPCON(5, 6)

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

181,205

15h

CCPR1L(3)

Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx

128,205

16h

CCPR1H(3)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx

128,205

17h

CCP1CON(3)

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0 0000 0000

127,205

18h

RCSTA(2)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

161,205

19h

TXREG(2)

EUSART Transmit Data Register

0000 0000

153

1Ah

RCREG(2)

EUSART Receive Data Register

0000 0000

158

1Bh

—

Unimplemented

—

1Ch

PWM1CON(3)

PRSEN

PDC6

PDC5

PDC4

PDC3

PDC2

PDC1

PDC0

0000 0000

145,205

1Dh

ECCPAS(3)

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0

PSSAC1

PSSAC0

PSSBD1

PSSBD0 0000 0000

142,205

1Eh

ADRESH(4)

A/D Result Register High Byte

xxxx xxxx

115,205

1Fh

ADCON0(4)

ADFM

VCFG

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

0000 0000

113,205

Legend:

– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note

MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F685/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK

Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

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