PIC12F1822-ISLASHMF datasheet(296/398 Pages) MICROCHIP

296 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 296

Preliminary

 2010 Microchip Technology Inc.

25.3.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 25-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 25-6. The fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRGL register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRGL register did not overflow by checking for 00h

in the SPBRGH register.

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 25-6. During ABD,

both the SPBRGH and SPBRGL registers are used as

a 16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

TABLE 25-6:

BRG COUNTER CLOCK RATES

FIGURE 25-6:

AUTOMATIC BAUD RATE CALIBRATION

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

Section 25.3.3

“Auto-Wake-up

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

3: During

the

auto-baud

process,

the

auto-baud counter starts counting at 1.

Upon

completion

the

auto-baud

sequence, to achieve maximum accuracy,

subtract 1 from the SPBRGH:SPBRGL

BRG16

BRGH

BRG Base

Clock

BRG ABD

Clock

FOSC/64

FOSC/512

FOSC/16

FOSC/128

FOSC/16

FOSC/128

FOSC/4

FOSC/32

Note:

During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

BRG Value

RX pin

ABDEN bit

RCIF bit

bit 0

bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto Cleared

Set by User

XXXXh

0000h

Edge #1

bit 2

bit 3

Edge #2

bit 4

bit 5

Edge #3

bit 6

bit 7

Edge #4

Stop bit

Edge #5

001Ch

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

SPBRGL

XXh

1Ch

SPBRGH

XXh

00h

RCIDL

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