PIC12F1822-ISLASHMF datasheet(277/398 Pages) MICROCHIP

277 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 277

PIC12F/LF1822/16F/LF1823

SSP1CON3: SSP1 CONTROL REGISTER 3

R-0/0

R/W-0/0

ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

DHEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock

0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock

bit 6

PCIE: Stop Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled(2)

bit 5

SCIE: Start Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Start or Restart conditions

0 = Start detection interrupts are disabled(2)

bit 4

BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:(1)

1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit

0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the

SSP1CON1 register is set, and the buffer is not updated

In I2C Master mode and SPI Master mode:

This bit is ignored.

In I2C Slave mode:

1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the

state of the SSP1OV bit only if the BF bit = 0.

0 = SSP1BUF is only updated when SSP1OV is clear

bit 3

SDAHT: SDA Hold Time Selection bit (I2C mode only)

1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL

0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL

bit 2

SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the

BCL1IF bit of the PIR2 register is set, and bus goes idle

1 = Enable slave bus collision interrupts

0 = Slave bus collision interrupts are disabled

bit 1

AHEN: Address Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the

SSP1CON1 register will be cleared and the SCL will be held low.

0 = Address holding is disabled

bit 0

DHEN: Data Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit

of the SSP1CON1 register and SCL is held low.

0 = Data holding is disabled

Note 1:

For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to

SSP1BUF.

This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

PIC12F1822-I/MF датащи(PDF) 277 Page - Microchip Technology

PIC12F1822-I/MF датащи(HTML) 277 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL