PIC12F1822-ISLASHMF datasheet(275/398 Pages) MICROCHIP

275 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 275

PIC12F/LF1822/16F/LF1823

SSP1CON1: SSP1 CONTROL REGISTER 1

R/C/HS-0/0

R/W-0/0

WCOL

SSP1OV

SSP1EN

CKP

SSP1M<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Bit is set by hardware

C = User cleared

bit 7

WCOL: Write Collision Detect bit

Master mode:

1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started

0 = No collision

Slave mode:

1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)

0 = No collision

bit 6

SSP1OV: Receive Overflow Indicator bit(1)

In SPI mode:

1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR

is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting

data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is

initiated by writing to the SSP1BUF register (must be cleared in software).

0 = No overflow

In I2C mode:

1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a “don’t care” in Transmit

mode (must be cleared in software).

0 = No overflow

bit 5

SSP1EN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins

In I2C mode:

1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)

0 = Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2C Slave mode:

SCL release control

1 = Enable clock

0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

In I2C Master mode:

Unused in this mode

bit 3-0

SSP1M<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4

0001 = SPI Master mode, clock = FOSC/16

0010 = SPI Master mode, clock = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled

0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0110 = I2C Slave mode, 7-bit address

0111 = I2C Slave mode, 10-bit address

1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4)

1001 = Reserved

1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))

1011 = I2C firmware controlled Master mode (Slave idle)

1100 = Reserved

1101 = Reserved

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF

When enabled, these pins must be properly configured as input or output.

When enabled, the SDA and SCL pins must be configured as inputs.

SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode.

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