PIC12F1822-ISLASHMF datasheet(251/398 Pages) MICROCHIP

251 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 251

PIC12F/LF1822/16F/LF1823

24.5.4

SLAVE MODE 10-BIT ADDRESS

RECEPTION

This section describes a standard sequence of events

for the MSSP1 module configured as an I2C Slave in

10-bit Addressing mode.

Figure 24-19 is used as a visual reference for this

description.

This is a step by step process of what must be done by

slave software to accomplish I2C communication.

Bus starts Idle.

Master sends Start condition; S bit of

SSP1STAT is set; SSP1IF is set if inter-

rupt-on-Start detect is enabled.

Master sends matching high address with R/W

bit clear; UA bit of the SSP1STAT register is set.

Slave sends ACK and SSP1IF is set.

Software clears the SSP1IF bit.

Software

reads

received

address

from

SSP1BUF clearing the BF flag.

Slave loads low address into SSP1ADD,

releasing SCL.

Master sends matching low address byte to the

Slave; UA bit is set.

Slave sends ACK and SSP1IF is set.

10. Slave clears SSP1IF.

11. Slave reads the received matching address

from SSP1BUF clearing BF.

12. Slave loads high address into SSP1ADD.

13. Master clocks a data byte to the slave and

clocks out the slaves ACK on the 9th SCL pulse;

SSP1IF is set.

14. If SEN bit of SSP1CON2 is set, CKP is cleared

by hardware and the clock is stretched.

15. Slave clears SSP1IF.

16. Slave reads the received byte from SSP1BUF

clearing BF.

17. If SEN is set the slave sets CKP to release the

SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

24.5.5

10-BIT ADDRESSING WITH ADDRESS OR

DATA HOLD

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSP1ADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCL line is held low are the

same. Figure 24-20 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 24-21 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

Note: Updates to the SSP1ADD register are not

allowed until after the ACK sequence.

Note: If the low address does not match, SSP1IF

and UA are still set so that the slave software

can set SSP1ADD back to the high address.

BF is not set because there is no match.

CKP is unaffected.

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