PIC12F1822-ISLASHMF datasheet(242/398 Pages) MICROCHIP

242 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 242

Preliminary

 2010 Microchip Technology Inc.

24.5.2

SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSP1STAT register is

cleared. The received address is loaded into the

SSP1BUF register and acknowledged.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSP1STAT

ter is set. The BOEN bit of the SSP1CON3 register

modifies this operation. For more information see

An MSSP1 interrupt is generated for each transferred

data byte. Flag bit, SSP1IF, must be cleared by soft-

ware.

When the SEN bit of the SSP1CON2 register is set,

SCL will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSP1CON1 register, except

sometimes in 10-bit mode. See Section 24.2.3 “SPI

Master Mode” for more detail.

24.5.2.1

7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSP1 module configured as an I2C Slave in

7-bit Addressing mode. All decisions made by hard-

ware or software and their effect on reception.

Figure 24-13 and Figure 24-14 is used as a visual

reference for this description.

This is a step by step process of what typically must

be done to accomplish I2C communication.

Start bit detected.

S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

Matching address with R/W bit clear is received.

The slave pulls SDA low sending an ACK to the

master, and sets SSP1IF bit.

Software clears the SSP1IF bit.

Software

reads

received

address

from

SSP1BUF clearing the BF flag.

If SEN = 1; Slave software sets CKP bit to

release the SCL line.

The master clocks out a data byte.

Slave drives SDA low sending an ACK to the

master, and sets SSP1IF bit.

10. Software clears SSP1IF.

11. Software reads the received byte from

SSP1BUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the Master.

13. Master sends Stop condition, setting P bit of

SSP1STAT, and the bus goes idle.

24.5.2.2

7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCL. These additional interrupts allow the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

This list describes the steps that need to be taken by

slave software to use these options for I2C commun-

cation. Figure 24-15 displays a module using both

address and data holding. Figure 24-16 includes the

operation with the SEN bit of the SSP1CON2 register

set.

S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

Matching address with R/W bit clear is clocked

in. SSP1IF is set and CKP cleared after the 8th

falling edge of SCL.

Slave clears the SSP1IF.

Slave can look at the ACKTIM bit of the

SSP1CON3 register to determine if the SSP1IF

was after or before the ACK.

Slave reads the address value from SSP1BUF,

clearing the BF flag.

Slave sets ACK value clocked out to the master

by setting ACKDT.

Slave releases the clock by setting CKP.

SSP1IF is set after an ACK, not after a NACK.

If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSP1IF.

11. SSP1IF set and CKP cleared after 8th falling

edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit of SSP1CON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSP1BUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

Note: SSP1IF is still set after the 9th falling edge of

SCL even if there is no clock stretching and

BF has been cleared. Only if NACK is sent to

Master is SSP1IF not set

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