PIC12F1822-ISLASHMF datasheet(239/398 Pages) MICROCHIP

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Preliminary

DS41413A-page 239

PIC12F/LF1822/16F/LF1823

TABLE 24-2:

I2C BUS TERMS

24.4.5

START CONDITION

The I2C specification defines a Start condition as a

transition of SDA from a high to a low state while SCL

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an Active state. Figure 24-10 shows wave

forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the

module samples the SDA line low before asserting it

low. This does not conform to the I2C Specification that

states no bus collision can occur on a Start.

24.4.6

STOP CONDITION

A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.

24.4.7

RESTART CONDITION

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop condi-

tion, a high address with R/W clear, or high address

match fails.

24.4.8

START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSP1CON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

TERM

Description

Transmitter

The device which shifts data out

onto the bus.

Receiver

The device which shifts data in

from the bus.

Master

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

Slave

The device addressed by the mas-

ter.

Multi-master

A bus with more than one device

that can initiate data transfers.

Arbitration

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle

No master is controlling the bus,

and both SDA and SCL lines are

high.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSP1ADD.

Write Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCL low to stall communication.

Bus Collision

Any time the SDA line is sampled

low by the module while it is out-

putting and expected high state.

Note: At least one SCL low time must appear

before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL

line stays high, only the Start condition is

detected.

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