PIC12F1822-ISLASHMF datasheet(241/398 Pages) MICROCHIP

241 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 241

PIC12F/LF1822/16F/LF1823

24.4.9

ACKNOWLEDGE SEQUENCE

The 9th SCL pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low indicated to the transmitter that the

device has received the transmitted data and is ready

to receive more.

The result of an ACK is placed in the ACKSTAT bit of

the SSP1CON2 register.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSP1CON2 reg-

ister is set/cleared to determine the response.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSP1CON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSP1STAT regis-

ter or the SSP1OV bit of the SSP1CON1 register are

set when a byte is received.

When the module is addressed, after the 8th falling

edge of SCL on the bus, the ACKTIM bit of the

SSP1CON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

24.5

I2C

SLAVE MODE OPERATION

The MSSP1 Slave mode operates in one of four

modes selected in the SSP1M bits of SSP1CON1 reg-

ister. The modes can be divided into 7-bit and 10-bit

Addressing mode. 10-bit Addressing modes operate

the same as 7-bit with some additional overhead for

handling the larger addresses.

Modes with Start and Stop bit interrupts operated the

same as the other modes with SSP1IF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

24.5.1

SLAVE MODE ADDRESSES

The SSP1ADD register (Register 24-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSP1BUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

The SSP Mask register (Register 24-5) affects the

address matching process. See Section 24.5.9

“SSP1 Mask Register” for more information.

24.5.1.1

I2C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

24.5.1.2

I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8

0’. A9 and A8 are the two MSb’s of the 10-bit address

and stored in bits 2 and 1 of the SSP1ADD register.

After the acknowledge of the high byte the UA bit is set

and SCL is held low until the user updates SSP1ADD

with the low address. The low address byte is clocked

in and all 8 bits are compared to the low address value

in SSP1ADD. Even if there is not an address match;

SSP1IF and UA are set, and SCL is held low until

SSP1ADD is updated to receive a high byte again.

When SSP1ADD is updated the UA bit is cleared. This

ensures the module is ready to receive the high

address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and pre-

pare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

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