MCP433X datasheet(62/88 Pages) MICROCHIP

62 / 88 page

MCP433X/435X

DS22242A-page 62

 2010 Microchip Technology Inc.

7.8.2

CONTINUOUS DECREMENTS

Continuous decrements are possible only when writing

to the volatile memory registers (address 00h, 01h, and

04h).

Figure 7-9 shows a continuous decrement sequence

for three continuous writes. The writes do not need to

be to the same volatile memory address.

When executing continuous Decrement commands,

the selected wiper will be altered from n to n-1 for each

Decrement command received. The wiper value will

decrement from the wiper’s full scale value (100h on

8-bit devices and 80h on 7-bit devices). Above the

wiper’s full scale value (8-bit = 101h to 1FFh,

7-bit = 81h to FFh), the Decrement command is

disabled. If the Wiper register has a zero scale value

(000h), then the wiper value will not decrement. See

Table 7-5 for additional information on the Decrement

command vs. the current volatile wiper value.

Decrement commands can be sent repeatedly without

raising CS until a desired condition is met.

When executing a continuous command string, the

Decrement command can be followed by any other

valid command.

The wiper terminal will move after the command has

been received (8th clock).

After the wiper is decremented to the desired position,

the CS pin should be forced to VIH to ensure that

“unexpected” transitions (on the SCK pin do not cause

the wiper setting to change). Driving the CS pin to VIH

should occur as soon as possible (within device

specifications) after the last desired decrement occurs.

FIGURE 7-9:

Continuous Decrement Command – SDI and SDO States.

X A

XX A

111111 1* 1111111 1* 1111111 1* 1 Note 1, 2

111111

0 Note 3, 4

111111

1111111

0 Note 3, 4

111111

1111111

0 Note 3, 4

(DECR COMMAND (n-1))

SDI

SDO

COMMAND BYTE

Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

3: Invalid Address/Command combination.

4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

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