TUSB9260

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SLLS962 – DECEMBER 2009

Table 2-4. Serial peripheral Interface (SPI) signals

TERMINAL

I/O

DESCRIPTION

NAME

NO.

SPI_SCLK

I/O

SPI clock

SPI_MOSI

I/O

SPI master out, slave in

SPI_MISO

I/O

SPI master in, slave out

SPI_CS0

I/O

Primary SPI chip select for Flash RAM

SPI_CS[2:1]/

SPI chip select. SPCI chip selects for additional peripherals. When not used for SPI chip selects

I/O

they may be used as general purpose I/O.

GPIO[11:10]

Table 2-5. Test and Miscellaneous Signals

TERMINAL

I/O

DESCRIPTION

NAME

No.

JTAG_TCK

I/O

JTAG test clock

JTAG_TDI

I/O

JTAG test data in

JTAG_TDO

I/O

JTAG test data out

JTAG_TMS

I/O

JTAG test mode select

JTAG_RSTN

I/O

JTAG reset

GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART

GPIO9/UART_TX

I/O

channel. This pin defaults to a general purpose output.

GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART

GPIO8/UART_RX

I/O

channel. This pin defaults to a general purpose output.

GPIO[7:0]

I/O

GPIO input/outputs. These pins are configurable as general purpose input/outputs.

PWM[1:0]

I/O

PWM input/outputs. These pins provide PWM capabilities for example to drive status LEDs.

Table 2-6. Power Signals

TERMINAL

I/O

DESCRIPTION

NAME

NO.

VDD33

PWR

3.3 V power rail

VDDA

PWR

1.1 V analog power rail

VDD18

PWR

1.8 V power rail

VDD11

PWR

1.1 V power rail

VSS

PWR

Ground, digital

VSSOSC

PWR

Oscillator return

Copyright © 2009, Texas Instruments Incorporated

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