TUSB9260

www.ti.com

SLLS962 – DECEMBER 2009

2

Overview

2.1

Description

The TUSB9260 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the

necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass

storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives

and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In addition, to UASP

support the firmware implements the mass storage class bulk-only transport, and USB human interface

device interfaces.

The TUSB9260 ROM contains boot code that executes after a global reset which performs the initial

configuration required to load a firmware image from an attached SPI flash memory to local RAM. In the

absence of an attached SPI flash memory or a valid image in the SPI flash memory, the firmware will idle

and wait for a connection from a USB host through its HID interface which is also configured from the boot

code. The latter can be accomplished using a custom application or driver to load the firmware from a file

resident on the host system.

Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter

(AHCI) and the USB device controller.

The configuration of the AHCI includes allocation of memory for the command list and the FIS receive

area, programming of the port command list (CL) and frame information structure (FIS) base address

registers and enabling the port to receive FISs, as well as configuration of interrupt sources for event

notification such as device connections.

In addition, the configuration of the AHCI includes a port reset which initiates an out of band (OOB) TX

sequence from the AHCI link layer to determine if a device is connected, and if so negotiate the

connection speed with the device (3.0 Gbps or 1.5 Gbps).

The OOB TX sequence starts by transmitting a COMRESET to the device. If no COMINIT is detected after

a timeout period, the link transmits a COMRESET again, and continues the sequence until a COMINIT is

detected. When a COMINIT is detected from a device, the link transmits a COMWAKE to the device and

waits for the device to return a COMWAKE. Following the receipt of COMWAKE, the device should begin

speed negotiation by transmitting ALIGN primitives at the highest data rate; the speed negotiation is

completed by the host decoding the ALIGN (either 3 Gbps or 1.5 Gbps depending on the device). After

speed negotiation is complete, the OOB TX sequence is complete and the link and phy are in the ready

state. Note, the only time a COMINIT is expected is after the transmission of COMRESET; the receipt of

COMINIT at any other time is an unsolicited COMINIT which transitions the link layer to the beginning of

OOB TX sequence.

Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device

signature. This first D2H FIS is received by the link layer and copied to the port signature register. When

firmware is notified of the device connection it queries the device for capabilities using the IDENTIFY

DEVICE command. Firmware then configures the device as appropriate for its interface and features

supported, for example an HDD that supports native command queuing (NCQ).

The configuration of the USB device controller includes creation of the descriptors, configuration of the

device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT), allocation

of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and

receive packet data over the USB. In addition, the firmware provides any other custom configuration

required for application specific implementation, for example a HID interface for user initiated backup.

After USB device controller configuration is complete, if a SATA device was detected during the AHCI

configuration the firmware connects the device to the USB bus when VBUS is detected. According to the

USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter

U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0

high-speed or full-speed device depending on the speed supported by host or hub port.

Copyright © 2009, Texas Instruments Incorporated

Overview

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Product Folder Link(s): TUSB9260