HT68F03 datasheet(74/139 Pages) HOLTEK

74 / 139 page

HT66F03/HT66F04/HT68F03/HT68F04

Rev. 1.00

April 16, 2010

However a compare match from Comparator A will also

automatically clear the TnON bit and thus generate the

Single Pulse output trailing edge. In this way the CCRA

value can be used to control the pulse width. A compare

match from Comparator A will also generate a TM inter-

rupt. The counter can only be reset back to zero when

the TnON bit changes from low to high when the counter

restarts. In the Single Pulse Mode CCRP is not used.

The TnCCLR and TnDPX bits are not used in this Mode.

Capture Input Mode

To select this mode bits TnM1 and TnM0 in the TMnC1

ables the external signal to capture and store the pres-

ent value of the internal counter and can therefore be

used for applications such as pulse width measure-

ments. The external signal is supplied on the TP1 pin,

whose active edge can be either a rising edge, a falling

edge or both rising and falling edges; the active edge

transition type is selected using the TnIO1 and TnIO0

bits in the TMnC1 register. The counter is started when

the TnON bit changes from low to high which is initiated

using the application program.

When the required edge transition appears on the TP1

pin, the present value in the counter will be latched into

the CCRA registers and a TM interrupt generated. Irre-

spective of what events occur on the TP1 pin the coun-

ter will continue to free run until the TnON bit changes

from high to low. When a CCRP compare match occurs

the counter will reset back to zero; in this way the CCRP

value can be used to control the maximum counter

value. When a CCRP compare match occurs from Com-

parator P, a TM interrupt will also be generated.

Counting the number of overflow interrupt signals from

the CCRP can be a useful method in measuring long

pulse widths. The TnIO1 and TnIO0 bits can select the

active trigger edge on the TP1 pin to be a rising edge,

falling edge or both edge types. If the TnIO1 and TnIO0

bits are both set high, then no capture operation will take

place irrespective of what happens on the TP1 pin, how-

ever it must be noted that the counter will continue to

run.

As the TP1 pin is pin shared with other functions, care

must be taken if the TM is in the Input Capture Mode.

This is because if the pin is setup as an output, then any

transitions on this pin may cause an input capture oper-

ation to be executed. The TnCCLR and TnDPX bits are

not used in this Mode.

CCRP

Counter

Value

Counter

overflow

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TnON bit

Pause

Counter

Reset

TnPAU bit

Resume

Stop

Time

CCRA

Value

TM Capture Pin

TnIO1, TnIO0

Value

00 - Rising edge

01 - Falling edge

11 - Disable Capture

Active

edge

Active

edge

10 - Both edges

Active

edges

TnM1, TnM0 = 01

Capture Input Mode

Note:

1. TnM1, TnM0 = 01 and active edge set by TnIO1 and TnIO0 bits

2. TM Capture input pin active edge transfers counter value to CCRA

3. TnCCLR bit not used

4. No output function - TnOC and TnPOL bits not used

5. CCRP sets counter maximum value

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