PCF8811USLASH2DASLASH1 datasheet(36/81 Pages) NXP

36 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

36 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

The data pointer is automatically updated and the data is directed to the intended

PCF8811 device. If the D/C bit of the last control byte was set to logic 0, these command

bytes will be decoded and the setting of the device will be changed according to the

received commands. The acknowledgement after each byte is made only by the

addressed PCF8811. At the end of the transmission the I2C-bus master issues a STOP

condition (P) and switches back to the F/S-mode, however, to reduce the overhead of the

master code, it is possible that a master can link a number of Hs-mode transfers,

separated by repeated START conditions (Sr).

11.3 Command decoder

The command decoder identiﬁes command words that are received on the I2C-bus:

• pairs of bytes: information in second byte, ﬁrst byte determines whether information is

display or instruction data

• Stream of information bytes after Co = 0: display or instruction data depending on last

D/C

The most signiﬁcant bit of a control byte is the continuation bit Co. If this bit is at logic 1, it

indicates that only one data byte, either command or RAM data, will follow. If this bit is at

logic 0, it indicates that a series of data bytes, either command or RAM data, may follow.

The DB6 bit of a control byte is the RAM data/command bit D/C. When this bit is at logic 1,

it indicates that a RAM data byte will be transferred next. If the bit is at logic 0, it indicates

that a command byte will be transferred next.

12. Instructions

The PCF8811 interfaces via an 8-bit parallel interface, two different 3-line serial interfaces,

a 4-wire serial interface or an I2C-bus interface. Processing of the instructions does not

require the display clock.

Data accesses to the PCF8811 can be broken down into two areas: those that deﬁne the

operating mode of the device, and those that ﬁll the display RAM.

In the case of the parallel and 4-wire SPI interfaces, the distinction is the D/C pad. When

the D/C pad is at logic 0, the chip will respond to instructions as deﬁned in Table 10. When

the D/C bit is at logic 1, the chip will send data to the RAM.

When the 3-wire SPI, the 3-wire serial interface or the I2C-bus interface is used, the

distinction between instructions which deﬁne the operating mode of the device and those

that ﬁll the display RAM, is made respectively by the display data length instruction (3-line

SPI) or by the D/C bit in the data stream (3-line serial interface and I2C-bus interface).

There are 4 types of instructions. Those which:

1. Deﬁne the PCF8811 functions, such as display conﬁguration etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

In normal use, category 3 instructions are used most frequently.

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