PCA9537_5

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 05 — 7 May 2009

7 of 24

NXP Semiconductors

PCA9537

6.6 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the

state of the Output Port register. Care should be exercised if an external voltage is applied

to an I/O configured as an output because of the low-impedance paths that exist between

Remark: At power-on reset, all registers return to default values.

Fig 4.

Simplified schematic of IO0 to IO3

I/O pin

output port

register data

configuration

register

DQ

CK

Q

data from

shift register

write

configuration

pulse

output port

register

DQ

CK

write pulse

polarity inversion

register

DQ

CK

data from

shift register

write polarity

pulse

input port

register

DQ

CK

read pulse

input port

register data

polarity

inversion

register data

002aad723

FF

data from

shift register

FF

FF

FF

Q1

Q2

to INT