LPC3230 datasheet(39/73 Pages) NXP

39 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

39 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

Two 32-bit match registers are readable and writable by the processor. A match will result

in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be

triggered by a match event, and cause an external power supply to turn on all of the

operating voltages, as a way to startup after power has been removed.

The RTC block is implemented in a separate voltage domain. The block is supplied via a

separate supply pin from a battery or other power source.

The RTC block also contains 32 words (128 Bytes) of very low voltage SRAM. This SRAM

is able to hold its contents down to the minimum RTC operating voltage.

7.9.4.1

Features

• Measures the passage of time in seconds.

• 32-bit up and down seconds counters.

• Ultra-low power design to support battery powered systems.

• Dedicated 32 kHz oscillator.

• An output pin is included to assist in waking up when the chip has had power removed

to all functions except the RTC.

• Two 32-bit match registers with interrupt option.

• 32 words (128 Bytes) of very low voltage SRAM.

• The RTC and battery RAM power have an independent power domain and dedicated

supply pins, which can be powered from a battery or power supply.

Remark: The LPC3220/30/40/50 will run at voltages down to 0.9 V at frequencies below

14 MHz. However, the ARM core cannot access the RTC registers and battery RAM when

the core supply voltage is at 0.9 V and the RTC supply is at 1.2 V.

7.9.5 Enhanced 32-bit timers/external event counters

The LPC3220/30/40/50 includes six 32-bit Timer/Counters. The Timer/Counter is

designed to count cycles of the system derived clock or an externally-supplied clock. It

can optionally generate interrupts or perform other actions at speciﬁed timer values,

based on four match registers. The Timer/Counter also includes four capture inputs to trap

the timer value when an input signal transitions, optionally generating an interrupt.

7.9.5.1

Features

• A 32-bit Timer/Counter with a programmable 32-bit pre-scaler.

• Counter or Timer operation.

• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– continuous operation with optional interrupt generation on match

– stop timer on match with optional interrupt generation

– reset timer on match with optional interrupt generation

• Up to four external outputs corresponding to match registers, with the following

capabilities:

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