LPC3230 datasheet(21/73 Pages) NXP

21 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

21 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

Functional description

7.1 CPU and subsystems

7.1.1 CPU

NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a

Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB

instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor. The

ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the

virtual memory capabilities required to support the multi-programming demands of

modern operating systems. The basic ARM926EJ-S core V5TE instruction set includes

DSP instruction extensions for native Jazelle Java Byte-code execution in hardware. The

LPC3220/30/40/50 operates at CPU frequencies up to 266 MHz.

7.1.2 Vector Floating Point (VFP) coprocessor

The LPC3220/30/40/50 includes a VFP co-processor providing full support for

single-precision and double-precision add, subtract, multiply, divide, and

multiply-accumulate operations at CPU clock speeds. It is compliant with the IEEE 754

standard for binary Floating-Point Arithmetic. This hardware ﬂoating point capability

makes the microcontroller suitable for advanced motor control and DSP applications. The

VFP has 3 separate pipelines for Floating-point MAC operations, divide or square root

operations, and Load/Store operations. These pipelines operate in parallel and can

complete execution out of order. All single-precision instructions execute in one cycle,

except the divide and square root instructions. All double-precision multiply and

multiply-accumulate instructions take two cycles. The VFP also provides format

conversions between ﬂoating-point and integer word formats.

7.1.3 Emulation and debugging

The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial

port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG

port allows debugging of all chip features without impact to any pins that may be used in

the application.

7.1.3.1

Embedded ICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

Embedded ICE protocol converter. The Embedded ICE protocol converter converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel (DCC) function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or entering the

debug state.

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