LPC1759 datasheet(13/64 Pages) NXP

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LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

13 of 64

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus

dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of

two core buses allows for simultaneous operations if concurrent operations target different

devices.

The LPC1759/58/56/54/52/51 use a multi-layer AHB matrix to connect the ARM

Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptable/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,

and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual that can be found on official ARM website.

7.3 On-chip flash program memory

The LPC1759/58/56/54/52/51 contain up to 512 kB of on-chip flash memory. A new

two-port flash accelerator maximizes performance for use with the two fast AHB-Lite

buses.

7.4 On-chip SRAM

The LPC1759/58/56/54/52/51 contain a total of up to 64 kB on-chip static RAM memory.

This includes the main 32/16/8 kB SRAM, accessible by the CPU and DMA controller on a

higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a

separate slave port on the AHB multilayer matrix.

This architecture allows CPU and DMA accesses to be spread over three separate RAMs

that can be accessed simultaneously.

7.5 Memory Protection Unit (MPU)

The LPC1759/58/56/54/52/51 have a Memory Protection Unit (MPU) which can be used

to improve the reliability of an embedded system by protecting critical data within the user

application.

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