1.

General description

The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a

GTL

−/GTL/GTL+ bus.

The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling

receiver or as an LVTTL-to-GTL interface.

The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or

5 V CMOS inputs.

2.

Features

GTL

−/GTL/GTL+ driver

JESD22-A115, and 1000 V CDM per JESD22-CC101

3.

Quick reference data

[1]

GTL2012

2-bit LVTTL to GTL transceiver

Rev. 01 — 9 August 2007

Product data sheet

Table 1.

Quick reference data

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

input capacitance

-

2

2.5

pF

input/output capacitance

-

4.6

6

pF

-

3.4

4.3

pF

LOW-to-HIGH propagation delay

An to Bn; see Figure 4

-

2.8

5

ns

HIGH-to-LOW propagation delay

An to Bn; see Figure 4

-

3.4

7

ns

LOW-to-HIGH propagation delay

Bn to An; see Figure 5

-

5.2

8

ns

HIGH-to-LOW propagation delay

Bn to An; see Figure 5

-

4.9

7

ns