LTC1821 datasheet(5/20 Pages) LINER

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LTC2757

2757f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CLR Timing

t25

CLR Pulse Width Low

VDD = 2.7V to 3.3V

Write and Update Timing

I/O Valid to WR Rising Edge Set-Up

I/O Valid to WR Rising Edge Hold

WR Pulse Width

UPD Pulse Width

UPD Falling Edge to WR Falling Edge

No Data Shoot-Through

0ns

WR Rising Edge to UPD Rising Edge

(Note 12)

0ns

D/S Valid to WR Falling Edge Set-Up Time

WR Rising Edge to D/S Valid Hold Time

Readback Timing

t13

WR Rising Edge to Read Rising Edge

t14

Read Falling Edge to WR Falling Edge

(Note 12)

t15

Read Rising Edge to I/O Propagation Delay

CL = 10pF

t17

UPD Valid to I/O Propagation Delay

CL = 10pF

t18

D/S Valid to Read Rising Edge

(Note 12)

t19

Read Rising Edge to UPD Rising Edge

No Update

9ns

t20

UPD Falling Edge to Read Falling Edge

No Update

9ns

t22

READ Falling Edge to UPD Rising Edge

(Note 12)

t23

I/O Bus Hi-Z to Read Rising Edge

(Note 12)

0ns

t24

Read Falling Edge to I/O Bus Active

(Note 12)

CLR Timing

t25

CLR Pulse Width Low

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Continuous operation above the speciﬁed maximum operating

junction temperature may impair device reliability.

Note 3: Temperature Coefﬁcient is calculated by dividing the maximum

change in the parameter by the speciﬁed temperature range.

Note 4: R1 is measured from RIN to RCOM; R2 is measured from REF to

RCOM.

Note 5: Parallel combination of the resistances from REF to IOUT1 and from

REF to IOUT2. DAC input resistance is independent of code.

Note 6: Because of the proprietary SoftSpan switching architecture, the

measured resistance looking into each of the speciﬁed pins is constant for

all output ranges if the IOUT1 and IOUT2 pins are held at ground.

TIMING CHARACTERISTICS V

DD = 5V, V(RIN) = 5V unless otherwise speciﬁed. The l denotes speciﬁcations that

apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.

Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time

of 1.8μs can be achieved by optimizing the time constant on an individual

basis. See Application Note 120,

1ppm Settling Time Measurement for a

Monolithic 18-Bit DAC.

Note 8: Measured at the major carry transition, 0V to 5V range. Output

ampliﬁer: LT1468; CFB = 50pF.

Note 9: Zero-code to full-code transition; REF = 0V. Falling transition is

similar or better.

Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output

ampliﬁer = LT1468.

Note 11: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K

(Boltzmann constant), R = resistance (

Ω), T = temperature (°K), and B =

bandwidth (Hz).

Note 12: Guaranteed by design. Not production tested.

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