PTH05050WAST datasheet(3/22 Pages) TI

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ELECTRICAL CHARACTERISTICS

PTH05050W

SLTS213D – MAY 2003 – REVISED JUNE 2007

A = 25°C; VI = 5 V; VO = 3.3 V; CI = 100 µF, CO1 = 0 µF, CO2 = 0 µF, and Io = Iomax (unless otherwise stated)

PARAMETER

TEST CONDITIONS

PTH05050W

UNIT

MIN

TYP

MAX

Output current

0.8 V

≤ V

O≤ 3.6 V

°C, natural convection

6(1)

Input voltage range

Over IO range

4.5

5.5

VOadj

Output adjust range

Over IO range

0.8

3.6

VOtol

Set-point voltage tolerance

±2(2)

%Vo

∆Reg

temp

Temperature variation

–40

°C < T

A < 85°C

±0.5

%Vo

∆Reg

line

Line regulation

Over VI range

±10

∆Reg

load

Load regulation

Over IO range

±12

∆Reg

tot

Total output variation

Includes set-point, line, load, –40

°C ≤ T

A ≤ 85°C

±3(2)

%Vo

RSET = 698 Ω, Vo = 3.3 V

95%

RSET = 2.21 kΩ, Vo = 2.5 V

93%

RSET = 4.12 kΩ, Vo = 2.0 V

91%

Efficiency

IO = 4 A

RSET = 5.49 kΩ, Vo = 1.8 V

90%

RSET = 8.87 kΩ, Vo = 1.5 V

89%

RSET = 17.4 kΩ, Vo = 1.2 V

87%

RSET = 36.5 kΩ, Vo = 1.0 V

85%

Vo ripple (pk-pk)

20 MHz bandwidth, Co2 = 10 µF ceramic

20(3)

mVpp

IOtrip

Over-current threshold

Reset, followed by auto-recovery

ttr

1 A/µs load step,

Recovery time

µSec

Transient response

50 to 100% IOmax,

Vo over/undershoot

100

∆V

CO1 = 100 µF

IILtrack

Track input current (pin 2)

Pin to GND

–130(4)

µA

dVtrack/dt

Track slew rate capability

CO≤ CO(max)

V/ms

VI increasing

4.3

4.45

UVLO

Under-voltage lockout

VI decreasing

3.4

3.7

VIH

Input high voltage, Referenced to GND

Open(4)

VIL

Inhibit Control (pin 4)

Input low voltage, Referenced to GND

–0.2

0.6

IIL inhibit

Input low current, Pin 4 to GND

130

µA

Iin inh

Input standby current

Inhibit (pin 4) to GND, Track (pin 2) open

f s

Switching frequency

Over VI and IO ranges

550

600

650

kHz

External input capacitance

100(5)

µF

Non-ceramic

100(6)

3300(7)

Capacitance value

µF

CO1, CO2

External output capacitance

Ceramic

300

Equivalent series resistance (non-ceramic)

4(8)

Ω

MTBF

Reliability

Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign

106 Hrs

(1)

No derating is required when the module is soldered directly to a 4-layer PCB with 1 oz. copper.

(2)

The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a

tolerance of 1% with 100 ppm/

°C or better temperature stability.

(3)

The pk-pk output ripple voltage is measured with an external 10 µF ceramic capacitor. See the standard application schematic.

(4)

This control pin has an internal pull-up to the input voltage. If it is left open-circuit the module will operate when input power is applied. A

small, low leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an

external pull-up on this pin. For further information, consult the related application note.

(5)

A 100 µF input capacitor are required for proper operation. The capacitor must be rated for a minimum of 300 mA rms of ripple current.

(6)

An external output capacitor is not required for basic operation. Adding 100 µF of distributed capacitance at the load will improve the

transient response.

(7)

This is the calculated maximum. The minimum ESR limitation will often result in a lower value. When controlling the Track pin using a

voltage supervisor, CO(max) is reduced to 2200 µF. Consult the application notes for further guidance.

(8)

This is the typical ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 m

Ω as he minimum when using max-ESR values

to calculate.

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