CS43L22 datasheet(40/66 Pages) CIRRUS

40 / 66 page

DS792F2

CS43L22

Confidential Draft

3/4/10

7.4.6

MCLK Divide By 2

Divides the input MCLK by 2 prior to all internal circuitry.

Note:

In Slave Mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 38) is disabled.

7.5

Interface Control 1 (Address 06h)

7.5.1

Master/Slave Mode

Configures the serial port I/O clocking.

7.5.2

SCLK Polarity

Configures the polarity of the SCLK signal.

7.5.3

DSP Mode

Configures a data-packed interface format for the DAC.

Notes:

Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 41).

The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.

7.5.4

DAC Interface Format

Configures the digital interface format for data on SDIN.

Note:

Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on

page 41).

MCLKDIV2

MCLK signal into DAC

No divide

Divided by 2

Application:

“Serial Port Clocking” on page 29

543

M/S

INV_SCLK

Reserved

DSP

DACDIF1

DACDIF0

AWL1

AWL0

M/S

Serial Port Clocks

Slave (input ONLY)

Master (output ONLY)

INV_SCLK

SCLK Polarity

Not Inverted

Inverted

DSP

DSP Mode

Disabled

Enabled

Application:

“DSP Mode” on page 31

DACDIF[1:0]

DAC Interface Format

Left Justified, up to 24-bit data

I²S, up to 24-bit data

Right Justified

Reserved

Application:

“Digital Interface Formats” on page 30

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