WM8736

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 2.1 January 2001

14

SERIAL PROTOCOL

Bits 0 (I

bit 0 (I

(I

POLARITY OF LRCIN SELECT

Bit 1 (LRP) of register M3 is used to control the polarity of LRCIN (sample rate clock). When bit 1 is

low (LRP = 0), left channel data is assumed when LRCIN is in a high phase and right channel data is

assumed when LRCIN is in a low phase. When bit 1 is high (LRP = 1), the polarity assumption

is reversed.

INTERFACE CLOCKS AND SAMPLING RATES

Bits 6 (SF0) and 7 (SF1) of register M3 are used to control the sampling frequency, as shown in

Table 12.

SF0

SF1

SAMPLING FREQUENCY

0

0

44.1kHz group

22.05 / 44.1 / 88.2kHz

0

1

48kHz group

24 / 48 / 96kHz

1

0

32kHz group

16 / 32 / 64kHz

1

1

Reserved

Not defined

Table 12 Sampling Frequencies

INFINITE ZERO DETECTION

Bit 8 (IZD) in register M3 controls operation of the automute function. If IZD (Infinite Zero Detect) is

high, 1024 consecutive zero audio samples will force the ouput to zero. See Figure 6. Note that the

control of pin MUTE also affects automute operation. To turn off automute, pin MUTE must be held

low as well as IZD being low (default).