WM8736

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 2.1 January 2001

12

REGISTER NAME

BIT NAME

DEFAULT

DESCRIPTION

Register M0

A[3:0] = 0000

AL[7:0]

LDL

1111 1111

0

Attenuation data for left channel DAC 0

Attenuation data load control for left channel DAC 0

Register M1

A[3:0] = 0001

AR[7:0]

LDR

1111 1111

0

Attenuation data for right channel DAC 0

Attenuation data load control for right channel DAC 0

Register M2

A[3:0] = 0010

MU

DE

OPE

IW[1:0]

PL[3:0]

0

0

0

00

1001

Left and right DACs soft mute control

De-emphasis control

Left and right DACs operation control

Input audio word resolution

DAC output control

Register M3

A[3:0] = 0011

I

LRP

ATC

SF[1:0]

IZD

0

0

0

00

0

Audio data format select

Polarity of LRCIN (pin 4) Select

Attenuator control

Sampling rate select

Infinite zero detection circuit control and automute control

Register M4

A[3:0] = 0100

AL[7:0]

LDL

1111 1111

0

Attenuation data for left channel DAC 1

Attenuation data load control for left channel DAC 1

Register M5

A[3:0] = 0101

AR[7:0]

LDR

1111 1111

0

Attenuation data for right channel DAC 1

Attenuation data load control for right channel DAC 1

Register M6

A[3:0] = 0110

AL[7:0]

LDL

1111 1111

0

Attenuation data for left channel DAC 2

Attenuation data load control for left channel DAC 2

Register M7

A[3:0] = 0111

AR[7:0]

LDR

1111 1111

0

Attenuation data for right channel DAC 2

Attenuation data load control for right channel DAC 2

Register M8

Master Gain

A[3:0] = 1000

AM[7:0]

LDM

1111 1111

0

DAC attenuation data for all channels

Attenuation data load control for all channels

Table 8 Internal Register Mapping

DAC OUTPUT ATTENUATION

Registers M0 and M1 control the left and right channel attenuation of DAC 0. Registers M4 and M5

control the left and right channel attenuation of DAC 1. Registers M6 and M7 control the left and right

channel attenuation of DAC 2. Register M8 is a master register that can be used to control

attenuation of all channels.

Register M0 (A[3:0] = 0000) is used to control left channel 0 attenuation. Bits 0-7 (AL[7:0]) are used

to determine the attenuation level (Table 9). The level of attenuation is given by:

Attenuation = [20.log10 (Attenuation_Data/256)] dB

Eqn. 1

AX[7:0]

ATTENUATION LEVEL

00(hex)

-

∞dB (mute)

01(hex)

-48.16dB

::

::

::

FE(hex)

-0.07dB

FF(hex)

0dB

Table 9 Attenuation Control Levels

Bit 8 in register M0 (LDL) is used to control the loading of attenuation data in AL[7:0]. When LDL is

set to 0, attenuation data will be loaded into AL[7:0], but it will not affect the attenuation level until

LDL is set to 1.

Register M1 (A[1:0] = 01) is used to control right channel attenuation in the same manner.

Attenuation of DAC 1 and 2 are similarly controlled.

Bit 2 in register M3 (A[3:0] = 0011) is used to control the attenuator (ATC). When ATC is high, the

attenuation data loaded in the left channel program register is used for both the left and the right

channels. Therefore, DAC 0 attenuation data for left and right channels is read from register M0,

DAC 1 attenuation data for left and right channels is read from register M4 and DAC 2 attenuation

data for left and right channels is read from register M6. When ATC is low, attenuation data is read

from the individual left and right DAC registers.