WM8191 datasheet(25/27 Pages) WOLFSON

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Advanced Information

WM8191

WOLFSON MICROELECTRONICS LTD

AI Rev 3.1 April 2001

BIT

NAME(S)

DEFAULT

DESCRIPTION

LINEBYLINE

Selects line by line operation 0 = normal operation,

1 = line by line operation.

When line by line operation is selected MONO is forced to 1 and

CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals

are produced. Green and Blue PGAs are also disabled to save power.

ACYCNRLC

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC

input pin and the input multiplexer and offset/gain register controls.

0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of

input and gain/offset multiplexers,

1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin.

See Table 4, Colour Selection Description in Line-by-Line Mode for colour

selection mode details.

When auto-cycling is enabled, the RLC/ACYC pin cannot be used for

reset level clamping. The RLCINT bit may be used instead.

2FME

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit controls the input force mux mode:

0 = No force mux, 1 = Force mux mode. Forces the input mux to be

selected by FM[1:0] separately from gain and offset multiplexers.

See Table 4 for details.

3RLCINT

When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine

whether Reset Level Clamping is used.

0 = RLC disabled, 1 = RLC enabled.

5:4

INTM[1:0]

Colour selection bits used in internal modes.

00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

See Table 4 for details.

Setup

7:6

FM[1:0]

Colour selection bits used in input force mux modes.

00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

See Table 4 for details.

VSMPDET

0 = Normal operation, signal on VSMP input pin is applied directly to

Timing Control block.

1 = Programmable VSMP detect circuit is enabled. An internal

synchronisation pulse is generated from signal applied to VSMP input pin

and is applied to Timing Control block.

3:1

VDEL[2:0]

000

When VSMPDET = 0 these bits have no effect.

When VSMPDET = 1 these bits set a programmable delay from the

detected edge of the signal applied to the VSMP pin. The internally

generated pulse is delayed by VDEL MCLK periods from the detected

edge.

See Figure 18, Internal VSMP Pulses Generated for details.

Setup

POSNNEG

When VSMPDET = 0 this bit has no effect.

When VSMPDET = 1 this bit controls whether positive or negative edges

are detected:

0 = Negative edge on VSMP pin is detected and used to generate internal

timing pulse.

1 = Positive edge on VSMP pin is detected and used to generate internal

timing pulse.

See Figure 18 for further details.

Setup

3:0

SELDIS[3:0]

0000

Selective power disable register - activated when SELPD = 1.

Each bit disables respective cell when 1, enabled when 0.

SELDIS[0] = Red CDS, PGA

SELDIS[1] = Green CDS, PGA

SELDIS[2] = Blue CDS, PGA

SELDIS[3] = ADC

Table 7 Register Control Bits

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