Advanced Information

WM8191

WOLFSON MICROELECTRONICS LTD

AI Rev 3.1 April 2001

17

STB

DNA

RNW

OP[13:6]

Address

Data

Hi-Z

Hi-Z

Driven by WM8191

Driven Externally

Normal Output Data

Driven by WM8191

Normal Output Data

Figure 16 Parallel Interface Register Write

PARALLEL INTERFACE: REGISTER READ-BACK

Figure 17 shows register read-back in parallel mode. Read-back is initiated by writing the 6-bit

address (a5, 1, a3, a2, a1, a0) into OP[11:6] by pulsing the STB pin low. Note that a4 = 1 and pins

RNW and DNA are low. When RNW and DNA are high and STB is strobed again, the contents (d7,

d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on

OP[13:6], LSB on pin OP[6]. Until STB is pulsed low, the current contents of the ADC (shown as

Normal Output Data) will be present on OP[13:6]. Note that the register data becomes available on

the output data pins so OEB should be held low when read-back data is expected.

STB

DNA

RNW

OP[13:6]

Address

Hi-Z

Driven by WM8191

Driven Externally

Hi-Z

Normal Output Data

Read Data

Driven by WM8191

Normal Output Data

Figure 17 Parallel Interface Register Read-back

TIMING REQUIREMENTS

To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock

(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces

internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum

sample rates for the various modes are shown in Table 5.

PROGRAMMABLE VSMP DETECT CIRCUIT

The VSMP input is used to determine the sampling point and frequency of the WM8191. Under

normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling

frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on

the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal

may not be readily available. The programmable VSMP detect circuit in the WM8191 allows the

sampling point to be derived from any signal of the correct frequency, such as a CCD shift register

clock, when applied to the VSMP pin.

When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge

(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.

This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.

Figure 18 shows the internal VSMP pulses that can be generated by this circuit for a typical clock

input signal. The internal VSMP pulse is then applied to the timing control block in place of the

normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising

MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.